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91411 sy 20081002-s00010/70208 sy im no.a1229-1/18 specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage conditi on (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. LE25FW403A overview the LE25FW403A is an onboard programmable flash memory device with a 512k 8-bit configuration. it uses a single 3.0v power supply and supports the serial interface. it has three erase functions de pending on the size of memory area in which the data is to be erased: the chip erase function, the sector (64k bytes) erase function, and a page (256 bytes) erase function. a page program method is supported for data writing and it can program any amount of data from 1 to 256 bytes. the page program time depends on the number of bytes programmed and the ic provides a high-speed program time of 1.5ms (typ) when programming 256 bytes at one time. moreover, equipped with a page write function that allows anywhere from 1 to 256 bytes of data in a page to be rewritten, this device is optimal for applications that perform small- scale rewriting. features ? read/write operations enabled by single 3.0v power supply: 2.7 to 3.6v supply voltage range ? operating frequency : 30mhz ? temperature range : 0 to 70 c ? serial interface : spi mode 0, mode 3 supported ? sector size : 256 bytes/page sector, 64k bytes/sector ? page erase, sector erase, chip erase functions ? page program function (1 to 256 bytes/page), page write function (1 to 256 bytes/page) ? hardware protect function (lower 256 pages) ? hardware reset function continued on next page. ordering number : ena1229b cmos ic 4m-bit (512k 8) serial flash memory 30mhz spi bus * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd.
LE25FW403A no.a1229-2/18 continued from preceding page. ? highly reliable read/write number of rewrite times : 10 5 times page erase time : 10ms (typ.), 20ms (m ax.), number of rewrite times: 10 4 times or less : 25ms (typ.), 300ms (max.), number of rewrite times: 10 5 times or less sector erase time : 30ms (typ.), 500ms (max.) chip erase time : 300ms (typ.), 5s (max.) page program time : 1.5ms/256 bytes (typ.), 2.5ms/256 bytes (max.) page write time : 11ms (typ.), 22.5ms (max.), number of rewrite times: 10 4 times or less : 25ms (typ.), 300ms (max.), number of rewrite times: 10 5 times or less ? status functions ready/busy information ? data retention period : 20 years ? package : LE25FW403Att msop8 (225mil) package dimensions unit:mm (typ) 3276 figure 1 pin assignment si sc k reset cs so v ss v dd wp 1 2 3 4 8 7 6 5 top view 6.3 5.2 1.27 4.4 (0.7) (0.65) 0.5 0.125 1 4 8 5 0.35 0.08 0.85max sanyo : msop8(225mil)
LE25FW403A no.a1229-3/18 figure 2 block diagram table 1 pin description symbol pin name description sck serial clock this pin controls the data input/output timing. the input data and addresses are latched synchronized to t he rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. si serial data input the data and addresses are input from this pin, and latched internally synchronized to the rising edge of the serial clock. so serial data output the data stored insi de the device is output from this pin sy nchronized to the falling edge of the serial clock. cs chip select the device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. wp write protect lower 256 pages are protected when the logic level of this pin is low. reset reset the device resets when the logi c level of this pin is low. however, reset is disabled when write (erase, program, or page write) are being internally executed by the device. v dd power supply this pin supplies the 2.7 to 3.6v supply voltage. v ss ground 4m bit flash eeprom cell array y-decoder i/o buffers & data latches cs sck si reset wp so x- decoder address buffers & latches serial interface control logic
LE25FW403A no.a1229-4/18 table 2 command settings command 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle nth bus cycle read 03h a23-a16 a15-a8 a7-a0 0bh a23-a16 a15-a8 a7-a0 x page erase dbh a23-a16 a15-a8 x sector erase d8h a23-a16 x x chip erase c7h page program 02h a23-a16 a15-a8 a7-a0 pd *1 pd *1 pd *1 page write 0ah a23-a16 a15-a8 a7-a0 pd *1 pd *1 pd *1 write enable 06h write disable 04h power down b9h status register read 05h read silicon id 9fh *2 exit power down mode abh explanatory notes for table 2 x = don't care, h = hexadecimal notation, a23-a19 = don?t care for all commands even if cs is raised for longer than the bus cycle given in the command settings table, the command will be recognized. however, cs must be raised between one bus cycle and the next. *1. pd: program data. input any number of bytes of data from 1 to 256 bytes in 1-byte units. *2. after the first bus cycle, silicon id repeatedly outputs 62h (manufacturer code), 11h (device code), and 00h (dummy code). device operation the LE25FW403A features electrical on-chip erase functions using a single 3.0v power supply, that have been added to the eprom functions of the industry standard that support serial interfaces. interfacing and control are facilitated by incorporating the command registers inside the chip. the read, erase, program and other required functions of the device are executed through the command registers. the command addresses and data are latched for program, erase and write operations. figures 3 and 4 show the timing waveforms of the serial data input. first, at the falling cs edge the device is selected, and serial input is enabled for the commands, addresses, etc. these inputs are introduced internally starting with bit 7 in sync hronization with the rising sck edge. at this time, output pin is in the high-impedance state. the output pin is placed in th e low-impedance state when the data is output starting with bit 7 synchronized to the falling clock edge during read, status register read and silicon id. the LE25FW403A sup ports both serial interface spi mode 0 and spi mode 3. at the falling cs edge, spi mode 0 is automatically selected if the logic level of sck is low, and spi mode 3 is automatically selected if the logic level of sck is high. figure 3 serial input timing spi mode definition * spi mode 0: sck is low logic level when cs falls * spi mode 3: sck is high logic level when cs falls high impedance tdh tcph tds tcsh tcss cs data valid so si sck high impedance tclh tcls tclhi tcllo
LE25FW403A no.a1229-5/18 figure 4 serial output timing command definition "table 2 command settings" provides a lis t and overview of the commands. a detailed description of the functions and operations corresponding to each command is presented below. 1. read figure 5 shows the read timing waveforms. there are two read commands, the 4 bus cycle read and 5 bus cycle read. consisting of the first through fourth bus cycles, the 4 bus cycle read inputs the 24 -bit address following (03h) and the data in the designated address is output synchronized to sck. the data is output on th e falling clock edge of fourth bus cycle bit 0. consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8 dummy bits following (0bh). the data is output using the falling clock edge of fifth bus cycle bit 0. the only difference between these two commands is whether the dummy bits in the fifth bus cycle are input. while sck is being input, the address is automatically incr emented inside the device and the corresponding data is output in sequence. if the sck input is continued after the data up to the highes t address (7ffffh) is output, the internal address returns to the lowest address (00000h) and data output is continued. by setting the logic level of cs to high, the device is deselected, and the re ad cycle ends. while the device is deselected, the output pin is in a high-impedance state. figure 5: read 4 bus read t ho t chz t clz si tv cs so sck data valid n+2 n+1 n cs high impedance data data data sc k so si 03h add. add. add. 15 msb msb msb 0 1 2 3 4 5678 23 16 24 31 39 47 8clk mode0 mode3 32 40
LE25FW403A no.a1229-6/18 5 bus read 2. status registers device status can be detected using status registers. table 3 gives the contents of status registers. table 3 status registers bit name logic function power-on time information bit0 rdy 0 ready 0 1 erase/program/write bit1 wen 0 write disabled 0 1 write enabled bit2 0 reserved bits 0 bit3 0 reserved bits 0 bit4 0 reserved bits 0 bit5 0 reserved bits 0 bit6 0 reserved bits 0 bit7 0 reserved bits 0 2-1. status register read the contents of the status registers can be read using the status register read command. this command can be executed even during the following operations. ? page erase ? sector erase ? chip erase ? page program ? page write figure 6 shows the timing waveforms of the status register read. consisting only of the first bus cycle, th e status register read command outputs the contents of the status register from bit 7 synchronized to the falling edge of the clock (sck) when (05h) is input. if the clock (sck) is continued after data up to rdy (bit 0) are output, the data is output by returning to the bit 7. data is output from the falling clock of the first bus cycle bit 0. n+2 n+1 n cs high impedance data data data sc k so si 0bh add. add. add. x 15 msb msb msb 0 1 2 3 4 5 6 7 8 23 16 24 31 32 39 40 47 48 55 mode3 mode0 8clk
LE25FW403A no.a1229-7/18 figure 6 status register read rdy (bit 0) the rdy register is for detecting the write (p rogram, erase and page write) end. when it is "1", the device is in a busy state, and when it is "0", it means that write is completed. wen (bit 1) the wen register is for detecting whethe r the device can perform write operations. if it is set to "0", the device will not perform the write operation even if the write command is input. if it is set to "1", the device can perform write operations in any area that is not protected. wen can be controlled using the write enable and write disable commands. by inputti ng the write enable command (06h), wen can be set to "1"; by inputting the write disable command (04h), it can be set to "0." in the following states, wen is automatically set to "0" in order to protect against unintentional writing. ? at power-on ? upon completion of page erase, sector erase or chip erase ? upon completion of page program ? upon completion of page write ? after hardware reset operations * if a write operation has not been performed inside the LE25FW403A because, for instance, the command input for any of the write operations (p age erase, sector erase, chip erase, page program, or page write) has failed or a write operation has been performed for a protected address, wen will retain the status established prior to the issue of the command concerned. furthermore, its state will not be changed by a read operation. bit2, bit3, bit4, bit5, bit6, bit7 these are reserved bits. 3. write enable write enable command sets the status register wen to ?1 .? the write enable command must be issued before performing any of the operations listed below. ? page erase ? sector erase ? chip erase ? page program ? page write figure 7 shows the timing waveforms. the write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). cs sc k si so msb msb msb 05h data data high impedance 8 3 2 1 07 6 5 415 23 mode3 mode0 8clk 16 data
LE25FW403A no.a1229-8/18 4. write disable the write disable command sets status register wen to ?0? to prohibit unintentional writing. figure 8 shows the timing waveforms when the write disable operation is performed. th e write disable command consists only of the first bus cycle, and it is initiated by inputting (04h). to exit write disable status (wen = 0), set we n to 1 using the write enable command (06h). figure 7 write enable figure 8 write disable 5. power-down the power-down command sets all the comm ands, with the exception of the command to exit from power-down, to the acceptance prohibited state (power-down) . figure 9 shows the timing waveform s. the power-down command consists only of the first bus cycle, and it is initiated by inputting (b9h). the power-down state is exited using the power-down exit command. figure 10 shows the timing waveforms of the power-down exit command. the power-down exit command consists only of the first bus cycle, and it is initia ted by inputting (abh). power-down state is exited also when power is tuned off or when hardware reset is performed. figure 9 power-down figure 10 exiting from power-down sc k si high impedance so cs 06h 0 1 2 3 4 5 6 7 mode3 mode0 8clk sc k si high impedance so cs 04h 0123 4 5 6 7 mode3 mode0 8clk sc k si high impedance so cs b9h 0 1 2 3 4 5 6 7 mode3 mode0 8clk sck si high impedance so cs a bh 0123 4 5 6 7 mode3 mode0 8clk t prb power down mode
LE25FW403A no.a1229-9/18 6. page erase page erase operation sets the memory cell data in any pages to ?1.? a page consists of 256 bytes. figure 11 shows the timing waveforms, and figure 21 shows a page erase flowchart. the page erase command consists of the first through f ourth bus cycles, and it is initiated by inputting the 24-bit addresses following (dbh). addresses a18 to a8 are valid, and all others are ?don't care.? after the command has been input, the erase operation starts from the rising edge of cs , and it ends automatically under the control of internal timer. al so, end of erase operation can be detected using status register. page erase time depends on the number of rewrites performed. the page erase time is 10ms (typ)/20ms (max) for up to 10 4 rewrites, and 25ms (typ)/300ms (max) for up to 10 5 rewrites. figure 11 page erase 7. sector erase sector erase operation sets the memory cell data in any sectors to ?1.? a sector consists of 64k bytes. figure 12 shows the timing waveforms, and figure 21 shows an erase flowchart. the sector erase command consists of the first through fo urth bus cycles, and it is initiated by inputting the 24-bit addresses following (d8h). addresses a18 and a16 are valid, and all others are ?don?t care.? after the command has been input, the erase operation starts from the rising edge of cs , and it ends automatically under the control of internal timer. al so, end of erase operation can be detected using status register. sector erase time is 30m s (typ)/500ms (max). if the lower 256 pages are being protected by setting the wp pin to low logic level, the sector erase operation cannot be performed on sectors including the lower 256 pages. figure 12 sector erase sc k si high impedance so cs self-timed erase cycle t pe add. dbh add. x 15 0 1 2 3 4 5678 23 16 24 31 mode3 mode0 8clk sc k si high impedance so cs self-timed erase cycle t se add. d8h add. x 15 0 1 2 3 4 5 6 7 8 23 16 24 31 mode3 mode0 8clk
LE25FW403A no.a1229-10/18 8. chip erase chip erase operation sets the memory cell data in all the sectors to ?1.? figure 13 shows the timing waveforms, and figure 21 shows an erase flowchart. the chip erase command consists only of the first bus cycle, and it is initiated by inputting (c7h). after the command has been input, the erase operation starts from the rising edge of cs , and it ends automatically under the control of internal timer. also, end of erase operation can be detected using status register. chip erase time is 300ms (typ)/5s (max). if the lower 256 pages are being protected by setting the wp pin to low logic level, the chip erase operation cannot be performed. figure 13 chip erase 9. page program page program operation can be used to program any number of bytes from 1 to 256 bytes for the erased pages (page addresses: a18 to a8). figure 14 shows the timing waveforms, and figure 22 shows a program flowchart. after cs is set low, the command code (02h) is input followed by the 24-bit addresses. addr esses a18 to a0 are valid. after this, the program data can be loaded until cs rises. if the loaded data exceeds 25 6 bytes, the 256 bytes loaded last are programmed. also, if the address of data being loaded reaches the last address of a page (a7 to a0: ffh), the device returns to the start address of the same page (a7 to a0: 00h). program data must be loaded in 1-byte units. the program opera tion is not performed if data is loaded in less than byte units and cs is set high. the page program time depends on the number of bytes programmed. when programming 256 bytes, the page program time is 1.5ms (typ)/2.5ms (max). figure 14 page program sc k si high impedance so cs self-timed erase cycle t che c7h 0 1 2 3 4567 mode3 mode0 8clk self-timed program cycle t pp sc k si high impedance so cs pd add. add. 02h add. pd 15 0 1 2 3 4 5 6 7 8 23 16 24 31 32 39 40 47 mode3 mode0 8clk pd 2079
LE25FW403A no.a1229-11/18 10. page write page write operation can be used to rewrite any number of bytes of data from 1 to 256 bytes in a page (page addresses: a18 to a8) without executing erase operation beforehand. figure 15 shows the timing waveforms, and figure 23 shows a flowchart. after cs is set low, the command code (0ah) is input followed by the 24-bit addresses. addresses a18 to a0 are valid. after this, re-write data can be loaded until cs rises. if loaded data exceeds 256 bytes, the 256 bytes loaded last are programmed. if the loaded data is less than 25 6 bytes, data not loaded on the same page is not rewritten. in addition, if the addres s of data being loaded reaches th e last address of a page (a7 to a0: ffh), the device returns to the start address of the same page (a7 to a0: 00h). rewrite data must be loaded in 1-byte units. the rewrite opera tion is not performed if data is loaded in less than byte units and cs is set high. the page write time depends on th e number of rewrites. the page write time is 11ms (typ)/22.5ms (max) for up to 10 4 rewrites, or 25ms (typ)/300ms (max) for up to 10 5 rewrites. figure 15 page write 11. silicon id read silicon id read allows manufacturer code and device code information to be read. figure 16 shows the timing waveforms, and table 6 gives the silicon id codes. table 6 silicon id codes output code manufacturer code 62h device code 11h dummy code 00h the silicon id read command consists of only the first bus cycle. if (9fh) is input, the manufacturer code 62h, device code 11h, and dummy code 00h are output in synchronization with the falling edge of sck. if sck input continues, the ic repeatedly outputs the data described above. data output is performed from the falling edge of clock at th e first bus cycle, bit 0. silicon id read is terminated by making cs go to high logic level. the silicon id read command is no t accepted during write operations. self-timed write cycle t pw sc k si high impedance so cs pd add. add. 0ah add. pd 15 0 1 2 3 4 5 6 7 8 23 16 24 32 39 40 47 mode3 mode0 8clk pd 2079
LE25FW403A no.a1229-12/18 figure 16 silicon id read 12. hardware reset a hardware reset can be performed by setting the reset pin to low logic level. figure 17 shows the timing waveforms. the hardware reset is disabled while write operation (erase, program, or page write) is being executed in the device. the pin so is held in the hi gh-impedance state while the device is in the reset mode. figure 17 hardware reset 13. hardware data protection lower 256 pages can be protected by setting the wp pin to low logic level. figure 18 shows the timing waveforms. in addition, the device has an internal power on reset function to prevent unintentional write operations at power on. figure 18 write protection t hrb cs t res reset t rp high impedance t wph cs so si sck high impedance t wps wp n+2 n+1 n cs high impedance 00h 11h 62h sck so si 9fh 15 0 1 2 3 45678 23 16 8clk mode0 mode3 31 msb msb msb
LE25FW403A no.a1229-13/18 in order to protect against unintentional writing at power- on, the LE25FW403A incorporates a power-on reset function. the following conditions must be met in order to ensure that the power reset circuit will operate stably. no guarantees are given for data in the event of an instantaneous power failure occurring during the writing period. figure 19 power-down timing 14. software data protection the LE25FW403A eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. ? when a write command is input and the rising cs edge timing is not in a bus cycle (8 clk units of sck) ? when the page program and page write data is not in 1-byte increments 15. power on v dd is applied to cs at power on to prevent unintentional write operations. to start read operations, turn the power on and input a command 100 s (t pu _read) after the power supply voltage has reached 2.7v or higher and has been stabilized. in addition, to start write operations, turn the power on and input a command 10ms (t pu _write) after power supply voltage has reached 2.7v or higher and has been stabilized. figure 20 power on timing 16. decoupling capacitor a 0.1 f ceramic capacitor must be provided to each device and connected between v dd and v ss in order to ensure that the device will operate stably. v dd (max) v dd (min ) v dd no device access allowed 0v v bot t pu _write t pu _read t pd program, erase and write command not allowed v dd (max) v dd (min) v dd chip selection not allowed 0v t pu _write t pu _read program, erase and write command not allowed read access allowed full access allowed
LE25FW403A no.a1229-14/18 specifications absolute maximum ratings parameter symbol conditions ratings unit maximum supply voltage with respect to v ss -0.5 to +4.6 v dc voltage (all pins) with respect to v ss -0.5 to v dd +0.5 v storage temperature tstg -55 to +150 c operating conditions parameter symbol conditions ratings unit operating supply voltage 2.7 to 3.6 v operating ambient temperature 0 to 70 c allowable dc operating conditions parameter symbol conditions ratings unit min typ max read mode operating current i ccr cs =0.1v dd , reset = wp =0.9v dd si=0.1v dd /0.9v dd , so=open, operating frequency=30mhz, v dd =v dd max 6ma write mode operating current i ccw v dd =v dd max 15 ma cmos standby current i sb cs = reset = wp =v dd -0.3v, si=v ss /v dd, so=open, v dd= v dd max 10 a input leakage current i li v in =v ss to v dd , v dd =v dd max 2 a output leakage current i lo v in =v ss to v dd , v dd =v dd max 2 a input low voltage v il v dd =v dd max -0.3 0.3v dd v input high voltage v ih v dd =v dd min 0.7v dd v dd +0.3 v output low voltage v ol i ol =100 a, v dd =v dd min 0.2 v i ol =1.6ma, v dd =v dd min 0.4 output high voltage v oh i oh =-100 a, v dd =v dd min v dd -0.2 v power-on timing parameter symbol ratings unit min max time from power-on to read operation t pu _read 100 s time from power-on to write operation t pu _write 10 ms power-down time t pd 10 ms power-down voltage v bot 0.2 v pin capacitance at ta=25 c, f=1mhz parameter symbol conditions max unit output pin capacitance c dq v dq =0v 12 pf input pin capacitance c in v in =0v 6 pf note: these parameter values do not represent the results of measurements undertaken for a ll devices but rather values for some of the sampled devices.
LE25FW403A no.a1229-15/18 ac characteristics parameter symbol ratings unit min typ max clock frequency f clk 30 mhz input signal rising/falling time t rf 20 ns cs setup time t css 10 ns cs hold time t csh 10 ns cs wait pulse width t cph 25 ns output high impedance time from cs t chz 15 ns data setup time t ds 5 ns data hold time t dh 5 ns sck setup time t cls 10 ns sck hold time t clh 10 ns sck logic high level pulse width t clhi 16 ns sck logic low level pulse width t cllo 16 ns output low impedance time from sck t clz 0 ns output data time from sck t v 8 15 ns output data hold time t ho 0 ns page erase cycle time number of rewrite times: 10 4 times or less t pe 10 20 ms number of rewrite times: 10 5 times or less 25 300 ms sector erase cycle time t se 30 500 ms chip erase cycle time t che 0.3 5 s page programming cycle time (256 bytes) t pp 1.5 2.5 ms page programming cycle time (n bytes) 0.04+ n*1.46/256 page write cycle time number of rewrite times: 10 4 times or less t pw 11 22.5 ms number of rewrite times: 10 5 times or less 25 300 ms wp setup time t wps 50 ns wp hold time t wph 50 ns reset setup time t res 10 ns reset pulse width t rp 100 ns hardware reset recovery time t hrb 1 s power-down recovery time t prb 25 ns ac test conditions input pulse leve l 0v, 3.0v input rising/falling time 5ns input/output timing level high data: 2.0v, low data: 0.8v output load 30pf note: as the test conditions for "typ", the measurements are conducted using 3.0v for v dd at room temperature.
LE25FW403A no.a1229-16/18 figure 21 erase flowchart start 05h set status register read command set page erase and small sector erase command address 1 address 2 start erase on rising edge of cs end of erase bit 0 = ?0? ? yes page/sector erase dummy 06h write enable dbh/d8h no * automatically placed in write disabled state at the end of the erase start 05h set status register read command set chip erase command start erase on rising edge of cs end of erase bit 0 = ?0? ? yes chip erase 06h write enable c7h no * automatically placed in write disabled state at the end of the erase
LE25FW403A no.a1229-17/18 figure 22 program flowchart figure 23 page write flowchart start 05h set status register read command set page program command address 1 address 2 start program on rising edge of cs end of programming yes bit 0= ?0? ? address 3 06h write enable 02h no * automatically placed in write disabled state at the end of the programming operation. program data 0 program data n start 05h set status register read command set page program command address 1 address 2 start program on rising edge of cs end of programming yes bit 0= ?0? ? address 3 06h write enable 0ah no * automatically placed in write disabled state at the end of the programming operation. rewrite data 0 rewrite data n
LE25FW403A no.a1229-18/18 ps this catalog provides information as of september, 2011. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility pr oducts, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these pr obab ilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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